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| 3936 DMOS THREE PHASE PWM MOTOR DRIVER ABSOLUTE MAXIMUM RATINGS at T A = +25C Load Supply Voltage, VBB......................... 50 V Output Current, IOUT .................................3 A* Logic Supply Voltage, VDD ........................ 7.0 V Logic Input Voltage Range, VIN ....................-0.3 V to VDD + 0.3 V (tW<30ns)................ -1.0V to VDD +1V Sense Voltage, VSENSE................................ 0.5 V Reference Voltage, VREF .............................. VDD Package Power Dissipation (TA = +25C), PD A3936SED ............................ 32C/W Operating Temperature Range, TA...............................-20C to +85C Junction Temperature, TJ ....................... +150C Storage Temperature Range, TS .............................-55C to +150C * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. Designed for Pulse Width Modulated (PWM) current control of three phase brushless DC motors, the A3936SED is capable of peak output currents to 3A and operating voltages to 50 V. Internal fixed off-time PWM current control timing circuitry can be configured to operate in slow, fast and mixed decay modes. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover current protection. Special power up sequencing is not required. The A3936 is supplied in a 44-lead plastic PLCC with a copper batwing tab (suffix `ED'). The power tab is at ground potential and needs no electrical isolation. Features y y y y y y y 3A, 50 V Continuous Output Rating Low RDS(ON) Outputs, typically 500 mohm source, 315 mOhm sink Configurable Mixed, Fast and Slow Current Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Tachometer Output for External Speed Control Loop 3936 Three Phase PWM Motor Driver FUNCTIONAL BLOCK DIAGRAM .22uf/50V .22uf/100V VREG CP2 CP1 VDD REGULATOR CHARGE PUMP VCP .22uf/50V VBB1 VBB2 OUTA OUTB OUTC LSS2 LSS1 SENSE .1uF ZERO CURRENT DETECT RS GND BUFFER/ DIVIDER REF TACH HBIAS BANDGAP OVERVOLTAGE UNDERVOLTAGE AND FAULT DETECT HAHA+ HALL HBHB+ HALL HCHC+ HALL Control Logic Comm Logic VREG VCP GATE DRIVE SLEEP DIR EXTMODE BRAKE SR ENABLE VDD OSC CURRENT SENSE BLANK PFD1 PFD2 PWM TIMER + - + - 3936 Three Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at TJ = +25C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Output Drivers Load Supply Voltage Range VBB Operating During Sleep Mode Output Leakage Current IDSS VOUT = VBB VOUT = 0 V Output On Resistance RDSON Source Driver, IOUT = -3A Sink Driver, IOUT = 3A Body Diode Forward Voltage VF Source Diode, IF = -3A Sink Diode, IF = 3A Motor Supply Current IBB fPWM < 50 kHz Charge Pump On, Outputs Disabled Sleep Mode Logic Supply Current IDD fPWM < 50 kHz Outputs Off Sleep Mode (Inputs below .5V) 9 0 - - - - - - - - - - - 4 2 - - - <1.0 <-1.0 - 50 50 20 -20 .55 .35 1.4 1.3 7 5 20 10 8 100 V V A A V V mA mA uA mA mA A Symbol Test Conditions Min. Typ. Max. Units Control Logic Logic Supply Voltage Range Logic Input Voltage VDD VIN(1) VIN(0) Logic Input Current (except ENABLE) Logic Input Current ENABLE Input Internal Oscillator IIN(1) IIN(0) IIN(1) IIN(0) fOSC VIN = VDD*.5 VIN = VDD*.2 VIN = VDD*.5 VIN = VDD*.2 OSC shorted to GND ROSC= 51K Operating 3 VDD*.5 - -20 -20 - - 3 3.4 4 4 5.0 - - <1.0 <-1.0 5.5 - VDD*.2 20 20 100 30 5 4.6 V V V A A A A MHz MHz 3936 Three Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at T J = +25C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Control Logic Buffer Input Offset Volt. VREF Input Voltage Range Reference Input Current Comparator Input Offset Volt. GM Error IREF VIO VERR (Note 3) Propagation Delay Times tpd VIO Operating VREF = VDD ,VBB=0 to 50V VREF = 0 V VREF = VDD VREF = .5V 50% TO 90%, SR Enabled PWM CHANGE TO SOURCE ON PWM CHANGE TO SOURCE OFF PWM CHANGE TO SINK ON PWM CHANGE TO SINK OFF Crossover Delay tCOD SR Enabled 600 50 600 50 300 750 150 750 100 600 1000 350 1000 150 1000 ns ns ns ns ns -4 -14 0.0 -.5 10 - 0 5 4 14 VDD 0.5 mV V A mV % % Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis TJ TJ Rising VDD - - 2.45 0.05 165 15 2.7 0.10 - - 2.95 - C C V V NOTES: 1. 2. 3. Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin. VERR =((VREF/10) - VSENSE)/(VREF/10) 3936 Three Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at T A = +25C, VBB = 50 V, VDD = 5.0 V fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Hall Logic Hall Input Current Common Mode Input Range AC Input Voltage Range Hysteresis Pulse Reject Filter IHALL VCMR VHALL VHYS TA= -20 to 85 deg C. VIN = 1.2V -1 .3 .120 10 3 5.5 30 8 0 1 2.5 A V Vp-p mV s Hall Bias Output Sat Voltage VHB IHB IOUT=40mA, TA= -20 to 85 deg C. .4 .5 40 V mA Tach Output VOL IOUT= 500uA .5 V NOTES: 1. 2. Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin. Commutation Truth Table 120 spacing HB HC + + + + + + + + + + + + + + + + + + + + + Outputs OUTB OUTC LO Z Z LO HI LO HI Z Z HI LO HI HI Z Z HI LO HI LO Z Z LO HI LO Z Z Z Z HA 1 2 3 4 5 6 1 2 3 4 5 6 DIR FOR FOR FOR FOR FOR FOR REV REV REV REV REV REV X X OUTA HI HI Z LO LO Z LO LO Z HI HI Z Z Z 3936 Three Phase PWM Motor Driver Functional Description VREG. The VREG pin should be decoupled with a 0.22 F capacitor to ground. This supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The Charge Pump is used to generate a supply above VBB to drive the source side DMOS gates. A 0.22 uF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 uF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high side DMOS devices. The VCP Voltage is internally monitored and in the case of a fault condition the outputs of the device are disabled. Extmode Logic. When using external PWM current control, the EXTMODE input determines the current path during the chopped cycle. With EXTMODE set low, fast decay mode, both the source and sink drivers are chopped OFF during the decay time (ENABLE=0). With EXTMODE high, slow decay mode, only the source driver turns off during the current decay time. EXTMODE 0 1 Decay Fast Slow Sleep Mode. The input pin SLEEP is dedicated to put the device into a minimum current draw mode. When asserted low, all circuits are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers. Current Regulation. Load current is regulated by an internal fixed off time PWM control circuit. When the outputs of the DMOS H-bridge are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF/(10*RSENSE) At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off time period. The current path during recirculation is determined by the configuration of slow/mixed decay mode and the synchronous rectification control setting. Fixed Off-Time. The 3936 is set for a fixed off time of 96 counts of the internal oscillator, typically 24 s with 4Mhz oscillator. Internal Current Control Mode. Input pins PFD1 and PFD2 determine the current decay method after an overcurrent event is detected at sense input. In slow decay mode both sink side drivers are turned on for the fixed off time period. Mixed decay mode starts out in fast decay mode for the selected percentage of the fixed off time, and then is followed by slow decay for the rest of the period. PFD2 0 0 1 1 PFD1 0 1 0 1 % tOFF 0 15 48 100 Decay Slow Mixed Mixed Fast Enable Logic. The Enable input terminal allows external PWM. ENABLE high turns ON the selected sinksource pair, enable low switches off the appropriate drivers and the load current decays. If the ENABLE pin is held high, the current will rise until it reaches the level set by the internal current control circuit. ENABLE 0 1 Outputs Source Chopped ON 3936 Three Phase PWM Motor Driver PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blank timer runs after the off time counter to provide the blanking function. The blank timer is reset when ENABLE is chopped or DIR is changed. For external PWM control, a DIR change or ENABLE ON will trigger the blanking function. The duration is adjusted by control input BLANK. BLANK 0 1 tBLANK 6/f OSC 12/f OSC Synchronous Rectification. Logic high applied to the SR terminal enables synchronous rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off time cycle, load current will recirculate according to the decay mode selected by control logic. The A3936 synchronous rectification feature will turn on the appropriate MOSFET(s)during the current decay and effectively short out the body diodes with the low Rdson driver. This will lower power dissipation significantly and can eliminate the need for external schottky diodes. Reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. Brake. Logic high to the brake terminal activates the brake function, logic low allows normal operation. Brake will turn all three sink drivers ON and effectively shorts out the motor generated BEMF. It is important to note that the internal PWM current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations of high speed and high inertial loads. Oscillator. The PWM timer is based on an internal oscillator set by a resistor connected from the OSC terminal to VDD. Typical value of 4Mhz is set with 51k resistor. FOSC = 204E9/ROSC. Tach. A tachometer signal is available for speed measurement. This open collector output toggles at each Hall transition. 3936 Terminal List Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name GND GND HA+ HAHB+ HBHC+ HCVDD REF GND GND GND BRAKE SENSE SR OUTA HBIAS VBB1 LSS1 OUTB GND GND GND LSS2 VBB2 TACH OUTC VCP CP1 CP2 SLEEP GND GND GND OSC VREG DIR ENABLE EXTMODE BLANK PFD2 PFD1 GND Pin Description Hall input Hall input Hall input Hall input Hall input Hall input Logic Supply Voltage Gm Reference Input Voltage Logic Input Sense Resistor Connection Logic Input (Disabled = Low, Active SR = High) DMOS H - Bridge A Connection for hall element neg side Load Supply Voltage Low Side Source connection DMOS H - Bridge B Low Side Source connection Load Supply Voltage Speed output DMOS H - Bridge C Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Logic input for SLEEP mode Oscillator Terminal Regulator decoupling Terminal Logic Input Logic Input Logic Input Logic Input Logic Input Logic Input Power Ground Tab 3936 This datasheet has been download from: www..com Datasheets for electronics components. |
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